According to foreign reports, AMD has been planning its multi-core chip development plan since 2001.

Its multi-core chips are different from Intel's core chips in structure. Each AMD company's 64 bit chips are individually equipped with a L2 cache of 512KB or 1MB, a built-in DDR 2 storage controller for a chip, and a super thread 8Gbits/ sec bus that is better than the common front end bus.

This design structure is closely linked to the processor core and storage subsystem, reducing the bottleneck of data pmission to a minimum.

However, due to the independence and relatively small capacity of the L2 cache, the chip becomes less flexible and affects the overall performance of the chip. This will result in a cache being overloaded and another fast cache not being put into use, and one of its cache is still accessing the main memory slowly, and the data it needs is already read to another cache.

AMD has accepted the criticisms of adding a shared universal L3 cache over each L2 cache unit.

Although AMD's existing products are already comparable to Intel's Meron, Conroe and Woodcrest, Intel's core chips seem to be slightly better in performance and power consumption.

The next generation of AMD's main chip structure will be K8L launched in the middle of next year.

It will include some new dual core desktop computer designs and a quad core server chip design.

In the mobile chip market, AMD will also launch a new Mobile Core design to replace Turion 64X2.

These upcoming products will improve the performance of the chip's floating point operation, improve the pmission speed of the hyper threading bus and enhance the function of the storage controller.

However, what are the functions of the new product are still unknown.